## Clock Signal # 50Mz
set_property -dict {PACKAGE_PIN G22 IOSTANDARD LVCMOS33} [get_ports {sys_clk}]
# create_clock -add -name sys_clk_pin -period 20.00 -waveform {0 10} [get_ports sys_clk]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets PAD_JTAG_TCLK]
# set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets PAD_JTAG_TCLK_TEE]

#reset 
set_property -dict { PACKAGE_PIN D26 IOSTANDARD LVCMOS33} [get_ports {PAD_MCURST}]

#LED8-LED1
set_property -dict { PACKAGE_PIN E25 IOSTANDARD LVCMOS33} [get_ports {PAD_GPIO_7}] 
set_property -dict { PACKAGE_PIN D25 IOSTANDARD LVCMOS33} [get_ports {PAD_GPIO_6}]
set_property -dict { PACKAGE_PIN D24 IOSTANDARD LVCMOS33} [get_ports {PAD_GPIO_5}]
set_property -dict { PACKAGE_PIN C26 IOSTANDARD LVCMOS33} [get_ports {PAD_GPIO_4}]
set_property -dict { PACKAGE_PIN C24 IOSTANDARD LVCMOS33} [get_ports {PAD_GPIO_3}]
set_property -dict { PACKAGE_PIN D23 IOSTANDARD LVCMOS33} [get_ports {PAD_GPIO_2}]
set_property -dict { PACKAGE_PIN A24 IOSTANDARD LVCMOS33} [get_ports {PAD_GPIO_1}]
set_property -dict { PACKAGE_PIN A23 IOSTANDARD LVCMOS33} [get_ports {PAD_GPIO_0}]



#===========================================
# C-SKY  JTAG interface: J8
#===========================================
set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS33} [get_ports {PAD_JTAG_TMS}]
set_property -dict {PACKAGE_PIN H12 IOSTANDARD LVCMOS33} [get_ports {PAD_JTAG_TCLK}]

# set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS33} [get_ports {PAD_JTAG_TMS_TEE}]
# set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS33} [get_ports {PAD_JTAG_TCLK_TEE}]
# set_property PACKAGE_PIN R6  [get_ports JTAG_TDI]
# set_property PACKAGE_PIN R7  [get_ports JTAG_TDO]
#set_property PACKAGE_PIN W15  [get_ports i_pad_jtg_trst_b]
#set_property PACKAGE_PIN AB15  [get_ports JTAG_NRST]

## UART
#TXD0 C12   RXD0 C14
set_property -dict { PACKAGE_PIN C12  IOSTANDARD LVCMOS33 } [get_ports { PAD_USI0_SD0 }] 
#IO_L3P_T0_DQS_AD1N_15 =UART_TXD
set_property -dict { PACKAGE_PIN C14  IOSTANDARD LVCMOS33 } [get_ports { PAD_USI0_SCLK }] 

#TXD1 D13   RXD0 B14
set_property -dict { PACKAGE_PIN D13  IOSTANDARD LVCMOS33 } [get_ports { PAD_USI1_SD0 }] 
set_property -dict { PACKAGE_PIN B14  IOSTANDARD LVCMOS33 } [get_ports { PAD_USI1_SCLK }]

#TXD2 D11   RXD2 D14
set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports {PAD_USI2_SCLK}]
set_property -dict {PACKAGE_PIN D11 IOSTANDARD LVCMOS33 } [get_ports {PAD_USI2_SD0}]

#User specified region constraints
#JTAG switch
set_property -dict { PACKAGE_PIN E12  IOSTANDARD LVCMOS33 } [get_ports { CORE_JTAG_SEL }] 


#FLSAH SPI
set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports {PAD_FLASHSPI_CLK}]
set_property -dict {PACKAGE_PIN C13 IOSTANDARD LVCMOS33 } [get_ports {PAD_FLASHSPI_TX }]
set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports {PAD_FLASHSPI_CSN}]
set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports {PAD_FLASHSPI_RX }]


#BANK 13
set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports {PAD_GPIO_8}]
set_property -dict {PACKAGE_PIN U20 IOSTANDARD LVCMOS33 } [get_ports {PAD_GPIO_9}]
set_property -dict {PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports {PAD_GPIO_10}]
set_property -dict {PACKAGE_PIN K25 IOSTANDARD LVCMOS33 } [get_ports {PAD_GPIO_11}]
set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports {PAD_GPIO_12}]
set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports {PAD_GPIO_13}]
set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports {PAD_GPIO_14}]
set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports {PAD_GPIO_15}]
set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports {PAD_GPIO_16}]
set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports {PAD_GPIO_17}]
set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports {PAD_GPIO_18}]
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports {PAD_GPIO_19}]
set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports {PAD_GPIO_20}]
set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports {PAD_GPIO_21}]
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports {PAD_GPIO_22}]
set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports {PAD_GPIO_23}]
# BANK15
set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports {PAD_GPIO_24}]
set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports {PAD_GPIO_25}]
set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports {PAD_GPIO_26}]
set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVCMOS33 } [get_ports {PAD_GPIO_27}]
set_property -dict {PACKAGE_PIN C19 IOSTANDARD LVCMOS33 } [get_ports {PAD_GPIO_28}]
set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS33 } [get_ports {PAD_GPIO_29}]
set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports {PAD_GPIO_30}]
set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVCMOS33 } [get_ports {PAD_GPIO_31}]

set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports {PAD_PWM_CH0}]
set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports {PAD_PWM_CH1}]
set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS33 } [get_ports {PAD_PWM_CH2}]
set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports {PAD_PWM_CH3}]
set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports {PAD_PWM_CH4}]
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports {PAD_PWM_CH5}]
set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports {PAD_PWM_CH6}]
set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports {PAD_PWM_CH7}]
set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports {PAD_PWM_CH8}]
set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports {PAD_PWM_CH9}]
set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports {PAD_PWM_CH10}]
set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports {PAD_PWM_CH11}]
set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports {PAD_PWM_FAULT}]

set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports {PAD_USI0_NSS}]
set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports {PAD_USI0_SD1}]

set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports {PAD_USI1_NSS}]
set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports {PAD_USI1_SD1}]

set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports {PAD_USI2_NSS}]
# set_property -dict {PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports {PAD_USI2_SCLK}]
# set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports {PAD_USI2_SD0}]
set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS33 } [get_ports {PAD_USI2_SD1}]

set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports {POUT_EHS}]
# synthesis COMBINATORIAL_LOOPS
set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets u_is_top/u_is_bus_top/u_ahb_matrix_7_12_main/x_matrix_arb/hmain1_cpu_m2_hrdata[0]]
set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets u_is_top/u_is_bus_top/u_ahb_matrix_7_12_main/x_matrix_arb/m0_cur_st[24]_i_6_n_0]
set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets x_pdu_top/x_sub_ls_top/sr_check_inst/srck_hrdata_o[0]]